nick.vhd

--------
-- This is what happens when you work in VHDL for 9 straight hours
-- after already working 4 hours this afternoon
--------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-- who am i?
entity nick is
  port (
    clk : in std_logic; -- the clock is ticking
    food : in std_logic; -- nick is hungry
    sleep : in std_logic; -- nick really, really needs to go to sleep
    work : out std_logic; -- nick is working
    quality : out unsigned(7 downto 0)); -- nick's work is not very good
end nick;

-- brain no worky
architecture brain of nick is
  signal time : unsigned(3 downto 0) := "1100";
begin brain
  engin: process (clk)
  begin process
    if clk = '1' and clk'event then
      if food = '0' and sleep = '0' then
        -- this makes no sense!
        quality <= quality - "0000" & time;
      end if;
      if quality = 0 then
        work <= '0';
      else
        work <= '1';
      end if;
    end if;
  end process engin;
end brain;