Day: March 23, 2004

——– — This is what happens when you work in VHDL for 9 straight hours — after already working 4 hours this afternoon ——– library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; — who am i? entity nick is port ( clk : in std_logic; — the clock is ticking food : in std_logic; — nick is…